module test3(
    input logic clk,
    output logic tx,
    input logic rx
);

logic dt[7:0];
logic rdy;

uart m_uart(.din(dt), .wr_en(rdy), .clk_50m(clk), .tx(tx), .rx(rx), .rdy(rdy), .rdy_clr(rdy), .dout(dt));

endmodule