module ind(
    input logic clk,
    input logic btn1,
    input logic btn2,
    input logic btn_sw,
    output logic led1,
    output logic led2,
    input logic rx,
    output logic tx
);

logic who_control, uart_inp, val;
// logic val = who_control ? uart_inp : btn_sw;
logic [1:0] out = { led2, led1 };
always_comb begin
    if(who_control)
        val = uart_inp;
    else
        val = btn_sw;

    case(val)
        0: out = { 1'b0, btn1 };
        1: out = { btn2, 1'b0 };
    endcase
end

logic rdy, rdy_clr, wr_en;
logic [7:0] din, dout;
uart m_uart(.din(din), .wr_en(wr_en), .clk_50m(clk), .tx(tx), .rx(rx), .rdy(rdy), .rdy_clr(rdy_clr), .dout(dout));

always_ff @(posedge rdy) begin
    case(dout)
        /* j */ 8'h6A: who_control <= ~who_control;
        /* l */ 8'h6C: uart_inp <= 0;
        /* r */ 8'h72: uart_inp <= 1;
    endcase

    din <= dout;
    rdy_clr <= 1;
    wr_en <= 1;
end

endmodule
