module test1(
    input logic clk,
    output logic rst,
    output logic led
);

reg [31:0] cnt;
logic clr_cnt;

assign clr_cnt = (cnt == 32'd25_000_000);

always @(posedge clk or negedge rst) begin
    if(!rst) cnt <= 32'h0;
    else if(clr_cnt) cnt <= 32'h0;
    else cnt <= cnt + 32'h1;
end

always @(posedge clk or negedge rst) begin
    if(!rst) led <= 1'b0;
    else if (clr_cnt) led <= ~led;
end

endmodule
